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    MD1812

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    HIGH SPEED QUAD MOSFET DRIVER

     

    产品信息

    MD1812 is a high-speed quad MOSFET driver. It is designed to drive two N and two P-channel high voltage DMOS FETs for medical ultrasound applications, but may be used in any application that needs a high output current for a capacitive load. The input stage of the MD1812 is a high-speed level translator that is able to operate from logic input signals of 1.8 to 5.0V amplitude. An adaptive threshold circuit is used to set the level translator threshold to the average of the input logic 0 and logic 1 levels. The level translator uses a proprietary circuit which provides DC coupling together with high-speed operation. The output stage of the MD1812 has separate power connections enabling the output signal L and H levels to be chosen independently from the driver supply voltages.As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and –5V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to ±2.0 amps depending on the supply voltages used and load capacitance. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly pre-charging the coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS. A built-in level shifter provides PMOS gate negative bias drive. This enables the user-defined damping control to generate return-to-zero bipolar output pulses.

      6.0ns rise and fall time

      2.0A peak output source/sink current

      1.8 to 5.0V input CMOS compatible

      Smart logic threshold

      Low jitter design

      Quad matched channels

      Drives two N and two P-channel MOSFETs

      Outputs can swing below ground

      Built-in level translator for negative gate bias

      User-defined damping for return-to-zero application

      Low inductance quad flat no-lead package

      Thermally-enhanced package

    电路图、引脚图和封装图

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    型号制造商描述购买
    MD1812K6-GATSHEATSINK25X25X15MML-TABT412 立即购买

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