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首页产品索引MC100EP52

MC100EP52

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 ECL Differential Clock/Data D Flip-Flop

制造商:ON

中文数据手册

产品信息

The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to V
) the outputs of the device will remain stable.
  • 330ps Typical Propagation Delay
  • Maximum Frequency > 4 GHz Typical
  • PECL Mode: V
  • = 3.0 V to 5.5 V with V
  • = 0 V
  • NECL Mode: V
  • = 0 V with V
  • = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at V
  • Pb-Free Packages are Available

电路图、引脚图和封装图

在线购买

型号制造商描述购买
MC100EP52MNR4GON 立即购买
MC100EP52DTR2GON 立即购买
MC100EP52DR2GON 立即购买
MC100EP52DGON 立即购买
MC100EP52DTGON 立即购买

技术资料

标题类型大小(KB)下载
AC Characteristics of ECL DevicesPDF896 点击下载
ECL Clock Distribution TechniquesPDF54 点击下载
Interfacing Between LVDS and ECLPDF121 点击下载
Designing with PECL (ECL at +5.0 V)PDF102 点击下载
The ECL Translator GuidePDF142 点击下载
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

应用案例更多案例

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