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    首页产品索引MC100LVEP14

    MC100LVEP14

    购买收藏
    5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer

    制造商:ON

    产品信息

    The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
    • 100 ps Device-to-Device Skew
    • 25 ps Within Device Skew
    • 400 ps Typical Propagation Delay
    • Maximum Frequency > 2 GHz Typical
    • PECL and HSTL Mode: V
    • = 2.375 V to 3.8 V with V
    • = 0 V
    • NECL Mode: V
    • = 0 V with V
    • = -2.375 V to -3.8 V
    • LVDS Input Compatible
    • Open Input Default State

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100LVEP14DTR2GONIC CLK BUFFER 2:5 2.5GHZ 20TSSOP 立即购买
    MC100LVEP14DTGONIC CLK BUFFER 2:5 2.5GHZ 20TSSOP 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

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