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    首页产品索引MC100EP16VA

    MC100EP16VA

    购买收藏
     Differential Driver / Receiver with High Gain

    制造商:ON

    产品信息

    The EP16VA is a world-class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. Q
    and Q
    bar outputs have a DC gain several times larger than the DC gain of an EP16.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    Under open input conditions (pulled to V
    ) internal input clamps will force the Q
    output LOW.
    Special considerations are required for differential inputs under No Signal conditions to prevent instability.
    The 100 Series contains temperature compensation.
    • 270 ps Typical Propagation Delay
    • Gain > 20
    • 20 mV Minimum Input Voltage Swing
    • Maximum Frequency > 3 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = - 3.0 V to - 5.5 V
    • Open Input Default State
    • V
    • Output

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100EP16VADTR2GONEP16VA 是一款世界一流的差分驱动器/接收器。该器件与 EP16 和 LVEP16 器件功能相同,只是带有高增益输出。QHG 和 QHGbar 输出的直流增益比 EP16 的直流增益高几倍。仅为此器件提供 VBB 引脚,即内部产生的供应电压。对于单端输入的情况,将未使用的差分输入联接至 VBB,作为开关参考电压。VBB 还可将 AC 耦合输入重偏置。使用时,通过 0.01 ?F 电容器对 VBB 和 VCC 进行去耦合,并将源/汲电流限制为 0.5 mA。不使用时,VBB 应保持开路。在开路输入条件下(拉至 VEE),内部输入箝位将强制 QHG 输出进入低电平。对于无信号条件下的差分输入,必须考虑特殊事项,以防不稳定性。100 系列包含温度补偿。 立即购买
    MC100EP16VADTGONEP16VA 是一款世界一流的差分驱动器/接收器。该器件与 EP16 和 LVEP16 器件功能相同,只是带有高增益输出。QHG 和 QHGbar 输出的直流增益比 EP16 的直流增益高几倍。仅为此器件提供 VBB 引脚,即内部产生的供应电压。对于单端输入的情况,将未使用的差分输入联接至 VBB,作为开关参考电压。VBB 还可将 AC 耦合输入重偏置。使用时,通过 0.01 ?F 电容器对 VBB 和 VCC 进行去耦合,并将源/汲电流限制为 0.5 mA。不使用时,VBB 应保持开路。在开路输入条件下(拉至 VEE),内部输入箝位将强制 QHG 输出进入低电平。对于无信号条件下的差分输入,必须考虑特殊事项,以防不稳定性。100 系列包含温度补偿。 立即购买
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    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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