首页产品索引MC100LVEL51

    MC100LVEL51

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     ECL Differential Clock D Flip-Flop

    制造商:ON

    产品信息

    The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3V V
    .
    The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop.
    The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V
    and the CLKbar input will be biased at V
    /2.
    • 475ps Propagation Delay
    • 2.8GHz Toggle Frequency
    • ESD Protection: >4 KV HBM, >200 V MM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 114 devices
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100LVEL51MNR4GONIC FF D-TYPE SNGL 1BIT 8DFN 立即购买
    MC100LVEL51DTR2GONIC FF D-TYPE SNGL 1BIT 8TSSOP 立即购买
    MC100LVEL51DR2GONIC FF D-TYPE SNGL 1BIT 8SOIC 立即购买
    MC100LVEL51DGONIC FF D-TYPE SNGL 1BIT 8SOIC 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

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