MC100EL17

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ECL Quad Differential Receiver

制造商：ON

中文数据手册

产品信息

The MC100EL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device.
Under open input conditions, the Dbar input will be biased at V
/2 and the D input will be pulled down to V
. This operation will force the Q output LOW and ensure stability.
The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
should be left open.

325 ps Propagation Delay
ESD Protection: > 2 KV HBM, > 100 V MM
The 100 series contains temperature compensation
PECL Mode Operating Range: V
= 4.2 V to 5.7 V with V
= 0 V
NECL Mode Operating Range: V
= 0 V with V
= -4.2 V to -5.7 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 141 devices
Pb-Free Packages are Available

电路图、引脚图和封装图

MC100EL17电路图

在线购买

型号	制造商	描述	购买
MC100EL17DWG	ON	IC RCVR QUAD DIFF LINE 20-SOIC	立即购买

技术资料

标题	类型	大小（KB）	下载
AC Characteristics of ECL Devices	PDF	896	点击下载
ECL Clock Distribution Techniques	PDF	54	点击下载
Interfacing Between LVDS and ECL	PDF	121	点击下载
Designing with PECL (ECL at +5.0 V)	PDF	102	点击下载
The ECL Translator Guide	PDF	142	点击下载
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	PDF	90	点击下载
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	PDF	71	点击下载
Storage and Handling of Drypack Surface Mount Device	PDF	49	点击下载

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