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    NBC12430

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     PLL Synthesized Clock Generator, Programmable, 3.3 V / 5.0 V (50 to 800 MHz)

    制造商:ON

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    产品信息

    The NBC12430 and NBC12430A are a general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N-output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 250 KHz, 500 KHz, 1.0 MHz, 2.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers settings. The PLL loop filter is fully integrated and does not require any external components.The NBC12430 is specified to operate across the commercial temperature range.The NBC12430A is specified to operate across the industrial temperature range.
    • Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak
    • 50 MHz to 800 MHz Programmable Differential PECL Outputs
    • Fully Integrated Phase-Lock-Loop with Internal Loop Filter
    • Parallel Interface for Programming Counter and Output Dividers During Power-Up
    • Minimal Frequency Overshoot
    • Serial 3-Wire Programming Interface
    • Crystal Oscillator Interface
    • Operating Range: VCC = 3.135 V to 5.25 V
    • CMOS and TTL Compatible Control Inputs
    • Drop-in Replacement for Motorola MC12430
    • Pb-Free Packages are Available

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    在线购买

    型号制造商描述购买
    NBC12430AMNGONNBC12430AMNG 立即购买
    NBC12430AFAGONIC CLOCK SYNTH 50-800MHZ 32-LQFP 立即购买
    NBC12430FAGONIC CLK PLL SYNC 50-800MHZ 32LQFP 立即购买
    NBC12430FNR2GONNBC12430FNR2G 立即购买
    NBC12430FAR2GON是通用的、基于PLL的合成时钟源。VCO将在400MHz至800MHz的频率范围内工作。VCO频率被发送到N输出分频器,可配置为提供1、2、4或8的分频比。VCO和输出频率可以使用并行或串行接口对配置逻辑进行编程。使用16MHz晶体,根据输出分频器设置,可实现250kHz、500kHz、1.0MHz、2.0MHz的输出频率步长。PLL环路滤波器完全集成,无需任何外部组件。 立即购买
    NBC12430FNGONNBC12430FNG 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载
    Interfacing with ECLinPSPDF72 点击下载

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