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    首页产品索引NB100LVEP222

    NB100LVEP222

    购买收藏
    15 Differential, ÷1 / ÷2, ECL / PECL, 2.5 V / 3.3 V

    制造商:ON

    产品信息

    The NB100LVEP222 is a low skew 2:1:15 differential div 1/div 2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. When the output banks are configured with the div 1 mode, data can also be distributed. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 4). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC/VCC0 supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in 2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC/VCC0 via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open
    • 20 ps Output-to-Output Skew
    • 85 ps Part-to-Part Skew
    • Selectable 1x or 1/2x Frequency Outputs
    • LVPECL Mode Operating Range: V
    • = 2.375 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -2.375 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Performance Upgrade to ON Semiconductor's MC100LVE222
    • V
    • Output

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    NB100LVEP222MNGONNB100LVEP222 是一款低歪曲率 2:1:15 差分 1 分频/2 分频 ECL 扇出缓冲器,适用于时钟分发。LVECL/LVPECL 输入信号对可用于差分配置或单端(VBB 输出参考旁通并联接一对未使用输入)。可以选择两个全差分时钟输入之一。在由 2、3、4 和 6 个差分对组成的四个输出组中,每组均可独立配置为输入频率的扇出 1X 或 1/2X。当输出组配置为 1 分频模式时,数据也可进行分发。LVEP222 可特别保证低输出-输出歪曲率。优化的设计、布局和处理最大程度降低了器件内和批次与批次之间的歪曲率。此器件是 MC100LVE222 的改善版本,具有更高速度能力且降低了歪曲率。fsel 引脚和 CLK_Sel 引脚为异步控制输入。任何更改都可能导致不确定的输出状态,需要 MR 脉冲来重新同步任何 1/2X 输出(参见图 4)。未使用的输出对应保持未端接(开路)以降低功耗和开关噪声。NB100LVEP222 与大多数 ECL 器件相同,可以 LVPECL 模式,基于正 VCC/VCC0 电源运行。因此,在 2.5/3.3 V 系统中使用 LVEP222 可实现高性能的时钟分发。在 PECL 环境串联或戴维南线路中,通常使用端接,因为它们无需额外的电源。有关使用 PECL 的更多信息,设计人员应参考应用说明 AN1406/D。 有关 SPICE 信号,请参考应用说明 AN1560/D。 仅为此器件提供 VBB 引脚,即内部产生的供应电压。对于单端 LVPECL 输入的情况,将未使用的差分输入联接至 VBB,作为开关参考电压。VBB 还可将 AC 耦合输入重偏置。使用时,通过一个 0.01 uF 电容将 VBB 和 VCC/VCC0 去耦合,并限制电流源或接收 0.5 mA 的电流。不使用时,VBB 应保持开路。 立即购买
    NB100LVEP222MNRGONIC CLK BUFFER 1:15 1GHZ 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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