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    首页产品索引MC10EP33

    MC10EP33

    购买收藏
     3.3 V / 5.0 V ECL ÷·4 Divider

    制造商:ON

    中文数据手册

    产品信息

    The MC10/100EP33 is an integrated divide by 4 divider. The differential clock inputs.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage.
    V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, V
    should be left open.
    The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP33's in a system.
    The 100 Series contains temperature compensation.
    • 320ps Propagation Delay
    • Maximum Frequency > 4 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Q Output will default LOW with inputs open or at V
    • V
    • Output
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC10EP33DGONMC10/100EP33 是一款集成式 4 分频分频器。差分时钟输入。仅为此器件提供 VBB 引脚,即内部产生的供应电压。对于单端输入情况,未使用的差分输入将作为开关参考电压联接 VBB。VBB 还可将 AC 耦合输入重偏置。使用时,通过一个 0.01 uF 电容将 VBB 和 VCC 去耦合,并限制电流源或接收 0.5mA 的电流。不使用时,VBB 应保持开路。重置引脚是异步的,在上升边进行断言。通电时,内部触发器将达到随机状态;重置可对系统中的多个 EP33 进行同步。100 系列包含温度补偿。 立即购买
    MC10EP33DTGON 立即购买
    MC10EP33DR2GONMC10/100EP33 是一款集成式 4 分频分频器。差分时钟输入。仅为此器件提供 VBB 引脚,即内部产生的供应电压。对于单端输入情况,未使用的差分输入将作为开关参考电压联接 VBB。VBB 还可将 AC 耦合输入重偏置。使用时,通过一个 0.01 uF 电容将 VBB 和 VCC 去耦合,并限制电流源或接收 0.5mA 的电流。不使用时,VBB 应保持开路。重置引脚是异步的,在上升边进行断言。通电时,内部触发器将达到随机状态;重置可对系统中的多个 EP33 进行同步。100 系列包含温度补偿。 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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