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    首页产品索引MC100LVEL17

    MC100LVEL17

    购买收藏
     Quad Differential Receiver

    制造商:ON

    产品信息

    The MC100LVEL17 is a 3.3 V ECL, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a -3.3 V or +3.3 V supply voltage.
    Under open input conditions, the Dbar input will be biased at V
    /2 and the D input will be pulled down to V
    . This operation will force the Q output LOW and ensure stability.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected toV
    as a switching reference voltage.V
    may also rebias AC coupled inputs. When used, decoupleV
    and V
    via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used,V
    should be left open.
    • 325 ps Propagation Delay
    • High Bandwidth Output Transitions
    • ESD Protection: >2 KV HBM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Q Output will Default LOW with Inputs Open or at V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 141 devices

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100LVEL17DWGONDifferential Receiver IC 20-SOIC 立即购买
    MC100LVEL17DWR2GONMC100LVEL17 是一款 3.3 V ECL,四路差分接收器。此器件功能相当于器件 E116,可基于 -3.3 V 或 +3.3 V 电源运行。在开路输入条件下,Dbar 输入将在 VCC/2 处偏置,D 输入将拉至 VEE。此操作将强制 Q 输出进入低电平,确保稳定性。仅为此器件提供 VBB 引脚,即内部产生的供应电压。对于单端输入的情况,将未使用的差分输入联接至 VBB, 作为开关参考电压。 VBB 还可将 AC 耦合输入重偏置。使用时,通过 0.01 F 电容器对 VBB 和 VCC 进行去耦合,并将源或汲电流限制为 0.5 mA。不使用时, VBB 应保持开路。 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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