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    首页产品索引MC100LVEL14

    MC100LVEL14

    购买收藏
    5 Clock Distribution Chip

    制造商:ON

    产品信息

    The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of -3.0 V to -3.8 V ( or 3.0 V to 3.8 V).
    The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input.
    The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    • 50 ps Output-to-Output Skew
    • Synchronous Enable/Disable
    • Multiplexed Clock Input
    • ESD Protection: >2 KV HBM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V
    • with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V
    • with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors on CLK
    • Q Output will Default LOW with Inputs Open or at V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: UL-94 code V-0 @ 1/8",
    • Oxygen Index 28 to 34
    • Transistor Count = 303 devices

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100LVEL14DWR2GONMC100LVEL14 是一款低歪曲率 1:5 分发芯片,明确适用于低歪曲率时钟分发应用。该器件可由差分或单端 ECL 驱动,如果使用正向电源,则由 PECL 输入信号驱动。LVEL14 可与 EL14 实现的功能和引脚兼容,但设计运行模式为 ECL 或 PECL,电压电源范围为 -3.0 V 至 -3.8 V(或 3.0 V 至 3.8 V)。LVEL14 具有多路复用时钟输入,可用于分发更低速扫描或测试时钟以及高速系统时钟。处于低电平(或保持开路并由输入下拉电阻拉为低电平)时,SEL 引脚将选择差分时钟输入。公共启用 (EN) 同步,因此输出仅在处于低电平状态时才启用/禁用。这样会避免当设备启用/禁用时产生短时钟脉冲,这种情况可能发生在异步控制中。内部触发器在输入时钟的下降边进行计时,因此,所有相关规格限制都参考到时钟输入的负边。仅为此器件提供 VBB 引脚,即内部产生的供应电压。对于单端输入的情况,将未使用的差分输入联接至 VBB,作为开关参考电压。VBB 还可将 AC 耦合输入重偏置。使用时,通过 0.01 5F 电容器对 VBB 和 VCC 进行去耦合,并将源电流或汲电流限制为 0.5 mA。不使用时,VBB 应保持开路。 立即购买
    MC100LVEL14DWGONMC100LVEL14 是一款低歪曲率 1:5 分发芯片,明确适用于低歪曲率时钟分发应用。该器件可由差分或单端 ECL 驱动,如果使用正向电源,则由 PECL 输入信号驱动。LVEL14 可与 EL14 实现的功能和引脚兼容,但设计运行模式为 ECL 或 PECL,电压电源范围为 -3.0 V 至 -3.8 V(或 3.0 V 至 3.8 V)。LVEL14 具有多路复用时钟输入,可用于分发更低速扫描或测试时钟以及高速系统时钟。处于低电平(或保持开路并由输入下拉电阻拉为低电平)时,SEL 引脚将选择差分时钟输入。公共启用 (EN) 同步,因此输出仅在处于低电平状态时才启用/禁用。这样会避免当设备启用/禁用时产生短时钟脉冲,这种情况可能发生在异步控制中。内部触发器在输入时钟的下降边进行计时,因此,所有相关规格限制都参考到时钟输入的负边。仅为此器件提供 VBB 引脚,即内部产生的供应电压。对于单端输入的情况,将未使用的差分输入联接至 VBB,作为开关参考电压。VBB 还可将 AC 耦合输入重偏置。使用时,通过 0.01 5F 电容器对 VBB 和 VCC 进行去耦合,并将源电流或汲电流限制为 0.5 mA。不使用时,VBB 应保持开路。 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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