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    MC100EP40

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     Phase-Frequency Detector, 3.3 V / 5 V, ECL Differential

    制造商:ON

    中文数据手册

    产品信息

    The MC100EP40 is a three-state phase-frequency detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V / 5 V power supply.
    When Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.
    When Reference (R) and Feedback (FB) inputs are 80 pSor less in phase difference, the Phase Lock Detect pin will indicate lock by a high state. The V
    (V
    , V
    bar , V
    , V
    bar ) pins offer an internal termination network for 50 line impedance environment shown in Figure 2. An external sinking supply of V
    -2 V is required on V
    pin(s). If you short the two differential V
    and V
    (or V
    and V
    bar ) together, you provide a 100 termination resistance that is compatible with LVDS signal receiver termination. For more information on termination of logic devices, see AND8020.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 F capacitor and limit current sourcing or sinkingto 0.5 mA. When not used, V
    should be left open.
    For more information on Phase Lock Loop operation, refer to AND8040.
    Special considerations are required for differential inputs under No Signal conditio
    • Maximum Frequency > 2 Ghz Typical
    • Fully Differential
    • Advanced High Band Output Swing of 400 mV
    • Theoretical Gain = 1.11
    • T
    • 97 pS Typical, F
    • 70 pS Typical
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • 50Ω Internal Termination Resistor
    • These are Pb-Free Devices

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100EP40DTR2GONMC100EP40DTR2G 立即购买
    MC100EP40DTGON3.3V / 5V ECL差分相位频率检测器 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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