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    首页产品索引MC100EP29

    MC100EP29

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     ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset

    制造商:ON

    中文数据手册

    产品信息

    The MC10/100EP29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.
    The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the Dbar input will pull down to V
    and the Dbar input will bias around V
    /2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.
    Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    The 100 Series Contains Temperature Compensation
    • Maximum Frequency > 3 GHz Typical
    • 500 ps Typical Propagation Delays
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • These are Pb−Free Devices

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100EP29MNGON 立即购买
    MC100EP29MNTXGONIC FF D-TYPE DUAL 1BIT 20QFN 立即购买
    MC100EP29DTR2GONMC10/100EP29 是一款双路主从型触发器。此器件提供全差分数据和时钟输入及输出。MC10/100EP29 与 MC10/100EL29 功能相同。当时钟为低电平时,数据进入主锁存,并在时钟输入正转换时传输至从锁存。差分输入采用特殊电路,从而确保在开路输入条件下的器件稳定性。在两个差分输入保持开路条件下,Dbar 输入将下拉至 VEE,并且 Dbar 输入将偏向于 VCC / 2。输出将进入指定状态,但根据触发器的启动方式,状态是随机的。两个触发器都提供异步超控“设置”和“重置”输入。请注意,设置和重置输入不能同时为高电平。VBB 引脚(内部产生的电源)仅可用于该器件。对于单端输入情况,将未使用的差分输入连接至 VBB,作为开关参考电压。VBB 还可重新偏置交流耦合输入。使用时,通过 0.01uF 电容器对 VBB 和 VCC 进行去耦合,并将源或汲电流限制为 0.5 mA。不使用时,VBB 应保持开路。100 系列包含温度补偿。 立即购买
    MC100EP29DTGON 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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