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首页产品索引MC100EP195

MC100EP195

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 3.3 V ECL Programmable Delay Chip

制造商:ON

中文数据手册

产品信息

NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and multiplexers as shown in the data sheet logic diagram. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(0:9) which are latched on chip by a high signal on the latch enable (LEN) control. The MC10/100EP195 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in the data sheet.
Because the EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs.
Select input pins D0-D10 may be threshold controlled by combinations of interconnects between V
(pin 7) and V
(pin 8) for CMOS, ECL, or TTL level signals. For CMOS input levels, leave V
and V
open. For ECL operation, short V
and V
(pins 7 and 8). For TTL level operation, connect a 1.5 V supply reference to V
and leave open V
pin. The 1.5 V reference voltage to V
pin can be accomplished by placing a 1.5k Ohm or 500 Ohm resistor between V
and V
for 3.3 V or 5.0 V power supplies, respectively.
The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01 uF capacitor and limit current sourcing o
  • Maximum Frequency > 1.2 Ghz Typical
  • Programmable Range: 2.2 ns to 12.2 ns
  • 10 ps Increments
  • PECL Mode Operating Range: V
  • = 3.0 V with V
  • = 0 V
  • NECL Mode Operating Range: V
  • = 0 V with V
  • = -3.0 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • A Logic High on the ENbar Pin Will Force Q to Logic Low
  • D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs.
  • V
  • Output Reference Voltage
  • Pb-Free Packages are Available

电路图、引脚图和封装图

在线购买

型号制造商描述购买
MC100EP195FAR2GONIC DELAY LN 1024TAP PROG 32LQFP 立即购买
MC100EP195MNGONNECL/PECL 输入转换。延迟部分由一个可编程的门极和多路复用器矩阵组成(如数据表逻辑图所示)。EP195 延迟增量的可数字选择分辨率约为 10 ps,最高 10.2 ns。10 个数据选择输入 D(0:9) 由锁存启用 (LEN) 控制上的高电平信号锁存在芯片上,通过这些数据选择输入 D 即可选择所需的延迟。MC10/100EP195 是一款可编程延迟芯片 (PDC),主要用于时钟去摆和计时调节。它具有一个差分可变延迟。与 D0 (LSB) 到 D9 (MSB) 相关的可变抽头数对应的大致延迟值如数据表所示。由于 EP195 设计为使用多路复用器链条,因此它具有 2.2 ns 的固定最小延迟。提供一个附加引脚 D10,用于级联多个 PDC,从而扩大可编程范围。级联逻辑允许完全控制多个 PDC。通过 CMOS、ECL 或 TTL 电平信号的 VEF(引脚 7)和 VCF(引脚 8)之间的互联组合,可对选择输入引脚 D0-D10 的阈值进行控制。对于 CMOS 输入电平,请将 VCF 和 VEF 保持开路。对于 ECL 运行,请将 VCF 和 VEF (引脚 7 和 8)保持短路。对于 TTL 电平运行,请将一个 1.5 V 参考电源连接至 VCF,并将 VEF 引脚保持开路。可在 VCF 和 VEE 之间放置 1.5 kΩ 或 500 Ω 电阻,分别用于 3.3 V 或 5.0 V 电源,从而让 VCF 引脚的参考电压达到 1.5 V。VBB 引脚作为内部产生的电源,仅可用于该器件。对于单端输入情况,将未使用的差分输入连接至 VBB,作为开关参考电压。VBB 还可重新偏置交流耦合输入。使用时,通过 0.01 F 电容器对 VBB 和 VCC 进行去耦合,并将源/汲电流限制为 0.5 mA。 立即购买
MC100EP195FAGONIC DELAY LN 1024TAP PROG 32LQFP 立即购买

技术资料

标题类型大小(KB)下载
AC Characteristics of ECL DevicesPDF896 点击下载
ECL Clock Distribution TechniquesPDF54 点击下载
Interfacing Between LVDS and ECLPDF121 点击下载
Designing with PECL (ECL at +5.0 V)PDF102 点击下载
The ECL Translator GuidePDF142 点击下载
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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