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    MC100E131

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     ECL 4-Bit D Flip-Flop

    制造商:ON

    中文数据手册

    产品信息

    The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (C
    ) LOW and using the Clock Enable (CEbar) inputs for clocking. Common clocking is achieved by holding the CEbar inputs LOW and using C
    to clock all four flip-flops. In this case, the CEbar inputs perform the function of controlling the common clock, to each flip-flop.
    Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry.
    Data enters the master when both C
    and CEbar are LOW, and transfers to the slave when either C
    or CEbar (or both) go HIGH.
    The 100 Series contains temperature compensation.
    • 1100MHz Min. Toggle Frequency
    • Differential Outputs
    • Individual and Common Clocks
    • Individual Resets (asynchronous)
    • Paired Sets (asynchronous)
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 V with V
    • = 0 V
    • 75k
    • Input Pulldown Resistors
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors
    • Metastability Time Constant is 200 ps.
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • ESD Protection: > 2 KV HBM, > 200 V MM
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 240 devices
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100E131FNGON 立即购买
    MC100E131FNR2GONMC10E/100E131 是一款带差分输出的四路主从型 D 类触发器。每个触发器可以通过保持公用时钟 (CC) 低电平和使用时钟启用 (CEbar) 输入来单独计时。公用计时通过保持 CEbar 输入低电平并使用 CC 来全部记录四个触发器的时间来实现。这种情况下,CEbar 输入对每个触发器执行控制公用时钟的功能。提供单独的异步重置 (R)。异步设置控件成对组合在一起,所选的配对反映了物理芯片的对称性。当 CC 和 CEbar 都为低电平时,数据进入主服务器,当 CC 或 CEbar(或两者)为高电平时,数据传输到从服务器。100 系列包含了温度补偿。 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

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