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    GD32F103C8T6STM32F103C8T6AMS1117-3.3STM32F407VET6OT8JI-111-50M

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    RC0402JR-070RLCC0402KRX7R8BB104CL21B105KBFNNNECL21A475KAQNNNERS-03K1002FTCL10A106MP8NNNC
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      首页产品索引MC100E131

      MC100E131

      购买收藏
       ECL 4-Bit D Flip-Flop

      制造商：ON

      中文数据手册

      MC100E131datasheet.pdf

      产品信息

      The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (C
      ) LOW and using the Clock Enable (CEbar) inputs for clocking. Common clocking is achieved by holding the CEbar inputs LOW and using C
      to clock all four flip-flops. In this case, the CEbar inputs perform the function of controlling the common clock, to each flip-flop.
      Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry.
      Data enters the master when both C
      and CEbar are LOW, and transfers to the slave when either C
      or CEbar (or both) go HIGH.
      The 100 Series contains temperature compensation.
      • 1100MHz Min. Toggle Frequency
      • Differential Outputs
      • Individual and Common Clocks
      • Individual Resets (asynchronous)
      • Paired Sets (asynchronous)
      • PECL Mode Operating Range: V
      • = 4.2 V to 5.7 V with V
      • = 0 V
      • 75k
      • Input Pulldown Resistors
      • NECL Mode Operating Range: V
      • = 0 V with V
      • = -4.2 V to -5.7 V
      • Internal Input Pulldown Resistors
      • Metastability Time Constant is 200 ps.
      • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
      • ESD Protection: > 2 KV HBM, > 200 V MM
      • Moisture Sensitivity Level 1
      • For Additional Information, see Application Note AND8003/D
      • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
      • Transistor Count = 240 devices
      • Pb-Free Packages are Available

      电路图、引脚图和封装图

      在线购买

      型号制造商描述购买
      MC100E131FNGONMC100E131FNG 立即购买
      MC100E131FNR2GONMC100E131FNR2G 立即购买

      技术资料

      标题类型大小（KB）下载
      AC Characteristics of ECL DevicesPDF896 点击下载
      ECL Clock Distribution TechniquesPDF54 点击下载
      Interfacing Between LVDS and ECLPDF121 点击下载
      Designing with PECL (ECL at +5.0 V)PDF102 点击下载
      The ECL Translator GuidePDF142 点击下载
      Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
      ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
      Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

      应用案例更多案例

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