首页产品索引NB100LVEP222

    NB100LVEP222

    购买收藏
    15 Differential, ÷1 / ÷2, ECL / PECL, 2.5 V / 3.3 V

    制造商:ON

    产品信息

    The NB100LVEP222 is a low skew 2:1:15 differential div 1/div 2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. When the output banks are configured with the div 1 mode, data can also be distributed. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 4). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC/VCC0 supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in 2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC/VCC0 via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open
    • 20 ps Output-to-Output Skew
    • 85 ps Part-to-Part Skew
    • Selectable 1x or 1/2x Frequency Outputs
    • LVPECL Mode Operating Range: V
    • = 2.375 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -2.375 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Performance Upgrade to ON Semiconductor's MC100LVE222
    • V
    • Output

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    NB100LVEP222MNGONIC CLK BUFFER 1:15 1GHZ 52QFN 立即购买
    NB100LVEP222MNRGONIC CLK BUFFER 1:15 1GHZ 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

    系列产品索引查看所有产品

    NC7SP17NCP134NCS2004NCP51200
    NV25320WFNUF4220NLX1G74NBSG72A
    NCV210NLSX3013NVMFD5C466NLNCV8401B
    NCV70627NB3F8L3010CNB2304ANTMFD5C446NL
    NCV7420NC7SV126NSVJ3557SA3NB3V60113G
    Copyright ©2012-2024 hqchip.com.All Rights Reserved 粤ICP备14022951号工商网监认证 工商网监 营业执照