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    MC10EP451

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     3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset

    制造商:ON

    中文数据手册

    产品信息

    The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to EE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.
    The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.
    The 100 Series contains temperature compensation.
    • 450 ps Typical Propagation Delay
    • Maximum Frequency > 3.0 GHz Typical
    • Asynchronous Master Reset
    • 20 ps Skew Within Device, 35 ps Skew Device-To-Device
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC10EP451MNGONIC FF D-TYPE SNGL 6BIT 32QFN 立即购买
    MC10EP451FAGONIC FF D-TYPE SNGL 6BIT 32LQFP 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    Interfacing with ECLinPSPDF72 点击下载
    Termination of ECL Logic DevicesPDF176 点击下载

    应用案例更多案例

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