首页产品索引MC100LVELT23

    MC100LVELT23

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     Translator, Dual Differential LVPECL to LVTTL

    制造商:ON

    产品信息

    The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal.
    The LVELT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external V
    reference, the LVELT23 does not require both ECL standard versions. The LVPECL inputs are differential; there is no specified difference between the differential input 10H and 100K standards. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a V
    of 3.3V.
    • 2.0ns Typical Propagation Delay
    • Maximum Frequency > 180 MHz
    • Differential LVPECL Inputs
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with GND= 0 V
    • 24 mA LVTTL Outputs
    • Flow Through Pinouts
    • Internal Pulldown Resistors
    • Q Output will default LOW with inputs open or at GND
    • ESD Protection: >1.5 KV HBM, >100 V MM
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 91 devices
    • Pb-Free Packages are Available

    电路图、引脚图和封装图

    在线购买

    型号制造商描述购买
    MC100LVELT23MNRGONXLATOR LVPECL/LVDS-LVTTL 8-DFN 立即购买
    MC100LVELT23DTRGONMixed Signal Translator Unidirectional 1 Circuit 2 Channel 8-TSSOP 立即购买
    MC100LVELT23DR2GONMixed Signal Translator Unidirectional 1 Circuit 2 Channel 8-SOIC 立即购买
    MC100LVELT23DGONMixed Signal Translator Unidirectional 1 Circuit 2 Channel 8-SOIC 立即购买
    MC100LVELT23DTGONIC TRANSLATOR DUAL 3.3V 8TSSOP 立即购买

    技术资料

    标题类型大小(KB)下载
    AC Characteristics of ECL DevicesPDF896 点击下载
    ECL Clock Distribution TechniquesPDF54 点击下载
    Interfacing Between LVDS and ECLPDF121 点击下载
    Designing with PECL (ECL at +5.0 V)PDF102 点击下载
    The ECL Translator GuidePDF142 点击下载
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
    Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

    应用案例更多案例

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