MC100EPT23

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Translator, Dual Differential LVPECL to LVTTL

制造商：ON

中文数据手册

产品信息

The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock and a data signal.
The EPT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external V
reference, the EPT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL input referenced from a V
of +3.3V.

1.5ns Typical Propagation Delay
Maximum Operating Frequency > 275MHz
24mA LVTTL Outputs
Operating Range: V
= 3.0 V to 3.6 V with GND = 0 V
Open Input Default State
Q Output will default LOW with inputs open or at GND
Pb-Free Packages are Available

电路图、引脚图和封装图

MC100EPT23电路图

在线购买

型号	制造商	描述	购买
MC100EPT23MNR4G	ON	IC XLATOR LV PECL-TTL DL 8-DFN	立即购买
MC100EPT23DTR2G	ON	Mixed Signal Translator Unidirectional 1 Circuit 2 Channel 8-TSSOP	立即购买
MC100EPT23DR2G	ON	Mixed Signal Translator Unidirectional 1 Circuit 2 Channel 8-SOIC	立即购买
MC100EPT23DTG	ON	IC XLATOR LVPECL-LVTTL 8-TSSOP	立即购买
MC100EPT23DG	ON	Mixed Signal Translator Unidirectional 1 Circuit 2 Channel 8-SOIC	立即购买

技术资料

标题	类型	大小（KB）	下载
AC Characteristics of ECL Devices	PDF	896	点击下载
ECL Clock Distribution Techniques	PDF	54	点击下载
Interfacing Between LVDS and ECL	PDF	121	点击下载
Designing with PECL (ECL at +5.0 V)	PDF	102	点击下载
The ECL Translator Guide	PDF	142	点击下载
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	PDF	90	点击下载
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	PDF	71	点击下载
Storage and Handling of Drypack Surface Mount Device	PDF	49	点击下载

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