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      首页产品索引MC100EPT21

      MC100EPT21

      购买收藏
       Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

      制造商：ON

      中文数据手册

      MC100EPT21datasheet.pdf

      产品信息

      The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.
      The V
      output allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, V
      output tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, V
      output is connected through a resistor to each input pin. If used, the V
      pin should be bypassed to V
      via a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use V
      for a single-ended direct connection.
      • 1.4ns Typical Propagation Delay
      • Maximum Frequency > 275 MHz Typical
      • 24mA TTL outputs
      • LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
      • The 100 Series Contains Temperature Compensation
      • V
      • Output
      • New Differential Input Common Mode Range

      电路图、引脚图和封装图

      在线购买

      型号制造商描述购买
      MC100EPT21MNR4GONIC XLATOR LVPECL-LVTTL 8-DFN 立即购买
      MC100EPT21DTR2GONIC XLATOR LVPECL-LVTTL 8-TSSOP 立即购买
      MC100EPT21DR2GONIC XLATOR LVPECL-LVTTL 8-SOIC 立即购买
      MC100EPT21DGONMixed Signal Translator Unidirectional 1 Circuit 1 Channel 8-SOIC 立即购买
      MC100EPT21DTGONIC XLATOR LVPECL-LVTTL DF 8TSSOP 立即购买

      技术资料

      标题类型大小（KB）下载
      AC Characteristics of ECL DevicesPDF896 点击下载
      ECL Clock Distribution TechniquesPDF54 点击下载
      Interfacing Between LVDS and ECLPDF121 点击下载
      Designing with PECL (ECL at +5.0 V)PDF102 点击下载
      The ECL Translator GuidePDF142 点击下载
      Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 点击下载
      ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 点击下载
      Storage and Handling of Drypack Surface Mount DevicePDF49 点击下载

      应用案例更多案例

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      MCP14A0052MOC8106MMIC4812MCP9501

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